NeoISA

CPU

because i like to deal with hardware and architecture, i want to document the ideas and progress here. i decided to separate the different development stages that contain a major change from the development itself. 
i started with the basicVM, which is supposed to clarify the idea behind the instruction set. it will be exciting with the next expansion stage ;)

basicVM

the basicVM, which is now available on github, should give you a first impression of what a stack machine that can also handle vectors can do. the following features were in the foreground during development: 

features:

• ssa stack based
• unified stack integer/float/bool and vector of these, up to a maximum length of 1 cache line - 512bit
• there is an arithmetic and a call stack
• scratchpad for the contents of the stack. stack holds the references and additional information such as the type
• atomic 8bit commands, which can be bundled to several.
• constants feeds the stack with parameters
• all commands which need operands, get them from the stack.
• all commands can handle vectors as operands, also load, store, jump and call
• there are no addressing modes. all address calculations have to be done by yourself.
• there is no rigid model regarding vector length or number of parallel units 

nextVM

the nextVM is in most points identical to the basicVM, but has a completely revised memory and program management.

features:

• ssa stack based
• unified stack integer/float/bool and vector of these, up to a maximum length of 1 cache line - 512bit
• there is an arithmetic and a call program-stack
• scratchpad for the contents of the stack. stack holds the references and additional information such as the type
• atomic 8bit commands, which can be bundled to several.
• constants feeds the stack with parameters
• all commands which need operands, get them from the stack.
• all commands can handle vectors as operands, also load, store, jump and call
• there are no addressing modes. all address calculations have to be done by yourself.
• there is no rigid model regarding vector length or number of parallel units 
• main memory is always accessed via a stack memory reference - stacksh
  • direct scratchpad: a memory block is reserved by scratchpad, and indirectly accessed via the stack element
  • direct memory: a memory block is mapped from main memory via a stack element, and indirectly addressed via the stack element
  • indirect memory: a memory block is mapped from main memory via a stack element, cached via scratchpad, and accessed indirectly via the stack element
• superblock program execution on the stack. superblock references are on the stack and can be managed and executed like the stack.

future features

• ssa stack cpu
  • unified 1bit-512bit (2^0 to 2^9)
  • each stack element holds additional data (type, size, state values)
  • separate values and call stacks
• in order
• extreme pipelined
• stash instead of cache - is more likely to be stacksh. stack + scratchpad = stack(ca)sh(e)
• no classic mmu.
  • linear 64bit adress space 
  • address translation at the transitions to the periphery- ram, io, ...
  • software tlb 
• atomic 8bit commands, which can also be bundled if it fits into the pipeline
  
  • bundles are h&t  coded
  • same commands can handle different types
  • superblock structure, jumps only to superblocks
  • bliss like front end 
• security model at memory level - minimum size is cacheline (512bit)
• inter-process communication with very low latency
• implicit threading